Synthesis of Electronic Circuits for Symmetric Functions
- 1 March 1958
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers
- Vol. EC-7 (1) , 57-60
- https://doi.org/10.1109/TEC.1958.5222097
Abstract
This paper develops a systematic method for the synthesis of electronic circuits which must realize symmetric Boolean functions. The ``fold-down'' method, originated by Shannon [1], solves the problem nicely for relay circuits. The electronic circuit, however, composed of ``and,'' ``or,'' and ``not'' elements, does not seem to incorporate the feature of symmetry as readily. It is shown that for symmetric functions a minimal-not condition exists, and that this form is a powerful tool for synthesis. The minimality is not actually proven, except for the case of fundamental symmetric functions. As with the minimal-or circuit, a minimal-not circuit does not necessarily imply the most economical realization, and the design procedure should take account of this fact.Keywords
This publication has 5 references indexed in Scilit:
- The Detection and Identification of Symmetric Switching Functions with the Use of Tables of CombinationsIEEE Transactions on Electronic Computers, 1956
- Detection of Group Invariance or Total Symmetry of a Boolean Function*Bell System Technical Journal, 1956
- Switching functions on an n-dimensional cubeTransactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics, 1954
- The recognition and identification of symmetric switching functionsTransactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics, 1954
- A symbolic analysis of relay and switching circuitsTransactions of the American Institute of Electrical Engineers, 1938