Explicit formulation of delays in CMOS VLSI

2 July 1987

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 23 (14) , 741-742
https://doi.org/10.1049/el:19870525

Abstract

An explicit formulation for the transient response of CMOS inverters is given, including load conditions and driving waveforms. Validation of the initial hypothesis is obtained through SPICE simulations. The results obtained show clear evidence of the influence of structural and parasitic parameters on propagation times, allowing fast optimisation of the data path.

Keywords

DATA PATH OPTIMISATION
PARASITIC PARAMETERS
PROPAGATION TIMES
CMOS INVERTERS
DELAYS
TRANSIENT RESPONSE
SPICE SIMULATIONS
DRIVING WAVEFORMS
VLSI
LOAD CONDITIONS

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