A Study of Variance Reduction Techniques for Estimating Circuit Yields
- 1 July 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 2 (3) , 180-192
- https://doi.org/10.1109/tcad.1983.1270035
Abstract
No abstract availableThis publication has 19 references indexed in Scilit:
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