Abstract
Through the use of band‐spreading techniques electrical power distribution networks become reliable and universal data links. For cost and performance reasons all digital solutions for the. construction of modems are paramount. The use of general purpose digital signal processors (DSP) is neither feasible nor cost‐effective. After a review of appropriate signalling schemes the key components for integration into an ASIC will be outlined. Within the transmitter section of the ASIC a programmable address counter together with a sample memory provides precise and fast signal synthesis. In the receiver section a fast front‐end is needed for correlation operations. Furthermore essential steps towards bit decision are performed. A typical ASIC, representing the heart of a power line modem, finally contains the following functional blocks: An 8 bit correlator with a minimum of four separate accumulators, a squarer with at least two additional accumulators forming the decision logic, and a programmable 10 bit address counter. VHDL‐based ASIC design was performed and fabrication took place in October 1994 within the EUROCHIP project. An ASIC incorporates 5250 gates with a power consumption below 50 mW. Modems have been built with different signalling schemes for data rates up to 2400 bits/s. Measurements revealed typical bit error rates below 106.

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