Novel architectures for declarative languages

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Abstract
Technology has made it possible to create huge numbers of single-chip computers at low cost. Because declarative languages allow parallel evaluation in a natural manner, one attractive possibility for novel architects is to ‘buy speed’ from recent technology by organising large numbers of chips to work in concert on the evaluation of a single declarative program. Following a brief introduction to the field of ‘declarative architectures’, some of the central issues are developed, and various novel architectures are discussed using a new classification based on the way work is distributed. The conclusion is that, even if the more extreme claims for ‘buying speed’ from VLSI for declarative languages fail to materialise, ‘super von Neumann’ implementations will make the new languages practicable very soon

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