Silicon-gate n-well CMOS process by full ion-implantation technology

1 September 1980

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 27 (9) , 1789-1795
https://doi.org/10.1109/t-ed.1980.20104

Abstract

A silicon-gate n-well CMOS process for an application of digital circuits operated by TTL compatible supply voltage was developed. Full ion-implantation technology, a new photolithography technique, n ⁺ -doped polysilicon gate which contain no boron impurities, and thin gate oxide of 65 nm can realize CMOS circuits of 2-µm gate length. Average impurity concentrations measured from substrate bias effect of MOSFET's and junction depth are in good agreement with those expected from impurity profiles calculated by a simple diffusion theory. So, the process design for CMOS circuits operated by any supply voltage is possible, by adjusting threshold voltages. The process can easily be extended to n-MOS/CMOS process (E/D MOS and CMOS on the same chip), if a photomask to fabricate depletion-type n-MOSFET's is provided.

Keywords

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