A scalable 32 Gb/s parallel data transceiver with on-chip timing calibration circuits

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Abstract
Inter-chip interconnect has become increasingly important due to the recent rapid development of switch fabric data network and symmetric multi-processing (SMP) server technologies. A high-speed parallel data transceiver megacell has low power, latency, and pin count for point-to-point interconnect between chips. Each macro includes a transmitter and a receiver. The aggregate bandwidth is 32 Gb/s, or 16 Gb/s in each direction. An on-chip timing calibration circuit performs data de-skewing and timing optimization. A transport layer handles error correction through the link. Low swing differential signaling further reduces noise and error probability, and therefore relaxes restrictions of board design. The entire macro is portable and scalable, and can be integrated with standard logic process. It also works well with standard packages such as EGA or QFP. Built-in self test (BIST) logic is implemented for product testing.

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