A punch-through isolated dynamic RAM cell

1 January 1978

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1978.189426

Abstract

A novel dynamic RAM Cell concept is introduced. The operation, charge storage mechanism and layout of the cell are similar in essence to the VMOS RAM Cell [1]. The novelty is in the use of a punch-through mechanism to address the cell. This results in a planar cell which may be fabricated using regular NMOS technology. The cell structure has the potential for very high density, low leakage and charge capacity comparable to the normal one-transistor cell. Measurements on the cell are compared with those on a one-transistor cell.

Keywords

DRAM CHIPS
THRESHOLD VOLTAGE
READ-WRITE MEMORY
DYNAMIC VOLTAGE SCALING
GEOMETRY
LEAKAGE CURRENT
LABORATORIES
INSTRUMENTS
MOS DEVICES
CIRCUITS

This publication has 0 references indexed in Scilit: