Analytical delay model of CMOS inverter including channel-length modulation

13 February 1992

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 28 (4) , 408-410
https://doi.org/10.1049/el:19920256

Abstract

An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.

Keywords

CHANNEL-LENGTH MODULATION
DELAY TIMES
HIGH-FIELD EFFECTS
DELAY MODEL
RISE TIME
SOURCE-DRAIN RESISTANCE
CMOS INVERTER
FALL TIME

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