Introduction of a new architecture for wafer integration through configuration hierarchies: resulting in practical monolithic self configuring wafer scale integration

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 92-101
https://doi.org/10.1109/icwsi.1990.63888

Abstract

Currently a monolithic self configuring test structure has been fabricated which achieves wafer scale integration levels through General Dynamics patented architecture, new technology and methodologies. The test structure uses a new double metal 3.0-micron GD/P:WSI CMOS technology. The device was not developed as a functional product, but rather as a test of the configuration manager, configuration management architecture and the new GD/P:WSI30G technology. The device consists of four quadrants of functionality clusters and configuration managers (CMs).

Keywords

INTEGRATED CIRCUIT INTERCONNECTIONS
POISSON EQUATIONS
WAFER SCALE INTEGRATION
INTEGRATED CIRCUIT NOISE
VERY HIGH SPEED INTEGRATED CIRCUITS
POWER SYSTEM INTERCONNECTION
POWER SYSTEM RELIABILITY
SILICON
CIRCUIT FAULTS
GEOMETRY

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