FAULT TOLERANCE AND DETECTION IN CHAOTIC COMPUTERS

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Abstract
We introduce a structural testing method for a dynamics based computing device. Our scheme detects different physical defects, manifesting themselves as parameter variations in the chaotic system at the core of the logic blocks. Since this testing method exploits the dynamical properties of chaotic systems to detect damaged logic blocks, the damaged elements can be detected by very few testing inputs, leading to very low testing time. Further the method does not entail dedicated or extra hardware for testing. Specifically, we demonstrate the method on one-dimensional unimodal chaotic maps. Some ideas for testing higher dimensional maps and flows are also presented.

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