Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 1 reference indexed in Scilit:
- A High Performance 0.25/spl mu/m CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993