A 3.3V 0.6 μm BiCMOS superscalar microprocessor
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 3.3 V 100 MHz BiCMOS 3.3M-transistor microprocessor in 163 mm/sup 2/ makes use of a four-layer metal 0.6 /spl mu/m technology. This device is an architecturally-equivalent second-generation superset of a previous CPU implemented in 0.8 /spl mu/m BiCMOS technology . It consists of a super scalar integer unit, a floating point unit, and separate 8 kB instruction and data caches. This implementation emphasizes several key areas.Keywords
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