Performance-oriented placement and routing for field-programmable gate arrays
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks Author(s) Alexander, M.J. Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA Cohoon, James P. ; Ganley, J.L. ; Robins, G.Keywords
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