Device down scaling and expected circuit performance
- 1 April 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 26 (4) , 421-429
- https://doi.org/10.1109/T-ED.1979.19444
Abstract
Based on appropriate down scaling of devices and reasonable extrapolation of present technological possibilities, circuit performance of several LSI technologies has been calculated. From a set of impurity distributions, oxide thickness, etc., process parameters have been derived, which have been converted into transistor-model parameters for use in a circuit simulation program. Although for every technology a substantial improvement in performance is predicted, MOS appears to benefit most from scaling down. The speed of ED-MOS eventually rivals that of ECL and the speed-power product that of I2L. Below 1 µm gate width a delay time of 100 ps and a speed-power product of 20 fJ are possible. I2L is by far the slowest technology, but it has the best packing density. Current densities in MOS approach that of ECL.Keywords
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