A generalized layout rule generator
- 1 April 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (2) , 589-591
- https://doi.org/10.1109/JSSC.1985.1052348
Abstract
As VLSI fabrication processes and systems become more complex, the number of layout rules required increases dramatically. A program is described that automatically creates and evaluates layout rules. The layout rules for a submicrometer CMOS process are generated and the variation of the density of a CMOS static RAM cell with process changes is illustrated.Keywords
This publication has 1 reference indexed in Scilit:
- An automated methodology for generating self-consistent layout rules for VLSI designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983