A nonoverlapping gate charge-coupling technology for serial memory and signal processing applications

1 February 1976

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 23 (2) , 271-275
https://doi.org/10.1109/t-ed.1976.18385

Abstract

Of the many technologies available to implement efficient and stable charge-coupled devices (CCD's), most employ a multilevel metal, overlapping gate approach. As a consequence, the CCD process becomes generally more complex and the resulting overlap capacitance can be embarrassing for serial memory applications. This paper describes a single level aluminium gate process, the notable features of which are simplicity, extremely high yield, low interphase capacitance, and very high packing density. Interelectrode spacings in the range 2000 Å-5000 Å are achieved. The performance capability is described in the context of an analog delay line.

Keywords

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