A subnanosecond 2000 gate array with ECL 100K compatibility

1 February 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 31 (2) , 139-143
https://doi.org/10.1109/t-ed.1984.21491

Abstract

This paper describes a subnanosecond gate array with 2000 gate complexity using an advanced bipolar process. The high performance of this process and the optimized circuit design have made it possible to achieve a 700-ps delay time for a basic ECL gate under a general usage condition of a 3 fan-in, 3 fan-out and 3-mm wiring length, in spite of a low power dissipation of 1.9 mW/gate. A 450-MHz typical toggle frequency has been obtained by using a series-gated flip-flop. Utilizing the integrated computer aided design (CAD) system, a quick and error-free design can be achieved. As a result, 100 percent routability has been attained for automatic placement and wiring in spite of 90 percent cell utilization. Low thermal resistance (6°C/W) packages are employed for this LSI chip to enable installation in an air cooled system.

Keywords

This publication has 0 references indexed in Scilit: