Hierarchical VLSI Routing--An Approximate Routing Procedure
- 1 April 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 4 (2) , 121-126
- https://doi.org/10.1109/tcad.1985.1270104
Abstract
This paper describes an approximate routing procedure. The procedure is quite general and could be applied to both printed circuit boards and integrated circuit chip wiring procedures where a hierarchical wiring scheme is utilized. This procedure has been incorporated in sperry's automatic gate array chip layout system.Keywords
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