8-bit micropower algorithmic A/D convertor

27 August 1987

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 23 (18) , 932-933
https://doi.org/10.1049/el:19870657

Abstract

A switched-capacitor algorithmic A/D convertor is described, in which the amplifier offset compensation is inherent to the circuit structure and the effect of clock-feedthrough is as low as 0.5 mV. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 8-bit resolution for 15 kHz sampling frequency, with only 350 μW power consumption.

Keywords

MICROWATT POWER CONSUMPTION
CLOCK-FEEDTHROUGH
350 MUW
MONOLITHIC IC
SWITCHED-CAPACITOR
ALGORITHMIC A/D CONVERTOR
15 KHZ
8 BIT
LOW-VOLTAGE CMOS TECHNOLOGY
ADC
AMPLIFIER OFFSET COMPENSATION

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