Deadlock avoidance for systolic communication

• 6 January 2003
• proceedings article
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• p. 252-260
• https://doi.org/10.1109/isca.1988.5235

Abstract

Keywords

• BUFFER STORAGE
• CELLULAR ARRAYS
• PARALLEL ARCHITECTURES
• PARALLEL PROGRAMMING
• QUEUEING THEORY
• SYSTEM RECOVERY
• BUFFERING
• COMPATIBLE QUEUE ASSIGNMENT
• CONSISTENT LABELING
• DEADLOCK AVOIDANCE
• DEADLOCK-FREE PROGRAMS
• PROGRAMMABLE SYSTOLIC ARRAYS
• QUEUE-INDUCED DEADLOCKS
• SPECIAL-PURPOSE SYSTOLIC ARRAYS
• SYSTOLIC COMMUNICATION
• SYSTOLIC MODEL OF COMMUNICATION
• COMPUTER SCIENCE
• CONCURRENT COMPUTING
• CONTRACTS
• CONVOLUTION