2.6 Gbyte/sec bandwidth cache/TLB macro for high-performance RISC processor
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 10.2/1-10.2/4
- https://doi.org/10.1109/cicc.1991.164046
Abstract
The authors describe an on-chip cache/TLB macro which can be integrated with highly concurrent RISC (reduced instruction set computer) processors. The macro incorporates TLB, a 16-kbyte instruction cache, and a 16-kbyte two-port data cache. It executes virtual-to-physical address translation and following physical cache access in 12 ns. The total bandwidth is 2.6 Gbyte/s at 80 MHz. A test chip was fabricated with 0.5- mu m double-polysilicon triple-metal CMOS technology.<>Keywords
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