Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

Top Cited Papers

Publisher Website

1 January 2000

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 90-95
https://doi.org/10.1109/lpe.2000.155259

Abstract

No abstract available

Keywords

This publication has 0 references indexed in Scilit: