18 GHz low-power CMOS static frequency divider
- 2 October 2003
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 39 (20) , 1433-1434
- https://doi.org/10.1049/el:20030932
Abstract
A pseudo-differential latch circuit is investigated. By removing the current source from the conventional source-coupled field-effect-transistor logic (SCFL) structure, the speed of the circuit can be improved. The pseudo-differential D-type flip-flop-based 2:1 static frequency divider, which can operate up to 18 GHz and consumes less than 4 mA from a 1.8 V supply, has been realised in 0.18 µm standard digital CMOS technology.Keywords
This publication has 2 references indexed in Scilit:
- SOI and bulk CMOS frequency dividers operatingabove 15 GHzElectronics Letters, 2001
- A 26.5 GHz silicon MOSFET 2:1 dynamic frequency dividerIEEE Microwave and Guided Wave Letters, 2000