A new realizability condition for limit cycle-free state-space digital filters employing saturation arithmetic

1 October 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems

Vol. 32 (10) , 1070-1071
https://doi.org/10.1109/tcs.1985.1085612

Abstract

A criterion for the absence of zero-input limit cycles in state-space digital filters employing saturation arithmetic is presented. An example is given, which brings out the novelity of the present approach.

Keywords

This publication has 6 references indexed in Scilit:

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