Fast hardware implementation of the Winograd Fourier transform algorithm

12 May 1983

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 19 (10) , 363-365
https://doi.org/10.1049/el:19830252

Abstract

We describe a novel partitioning of small Winograd DFTs into two identical subunits, each of which computes a real-input DFT. A bit-serial arithmetic single IC implementation in semicustom or custom LSI is described. A fast hardware WFTA is then proposed which is efficient for complex or real input data.

Keywords

FFT
REAL-INPUT DFT
CUSTOM LSI
WFTA
FAST HARDWARE IMPLEMENTATION
BIT-SERIAL ARITHMETIC SINGLE IC IMPLEMENTATION
COMPUTER INPUT DATA
WINOGRAD FOURIER TRANSFORM ALGORITHM
SEMICUSTOM LSI

This publication has 0 references indexed in Scilit: