Minimal area design of power/ground nets having graph topologies
- 1 December 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems
- Vol. 34 (12) , 1441-1451
- https://doi.org/10.1109/tcs.1987.1086084
Abstract
This paper deals with one aspect of routing power and ground nets in integrated circuits composed of modules, where the nets are routed in the channels between the modules. Constraints are assumed on allowable voltage drops for maintaining proper logic levels and switching speed. A procedure for determining the width of routes in power and ground multi-pad distribution systems having graph topologies is presented, where the objective is to minimize the area of the power and ground routes subject to several constraints, such as IR voltage drop and metal migration.Keywords
This publication has 9 references indexed in Scilit:
- The construction of minimal area power and ground nets for VLSI circuitsPublished by Association for Computing Machinery (ACM) ,1985
- Laying the Power and Ground Wires on a VLSI ChipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A Bus Router for IC LayoutPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- On routing for custom integrated circuitsPublished by Association for Computing Machinery (ACM) ,1982
- Augmented Lagrange Multiplier Functions and Duality in Nonconvex ProgrammingSIAM Journal on Control, 1974
- Electromigration and failure in electronics: An introductionProceedings of the IEEE, 1971
- Multiplier and gradient methodsJournal of Optimization Theory and Applications, 1969
- Electromigration failure modes in aluminum metallization for semiconductor devicesProceedings of the IEEE, 1969
- The Gradient Projection Method for Nonlinear Programming. Part II. Nonlinear ConstraintsJournal of the Society for Industrial and Applied Mathematics, 1961