Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

1 January 1993

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 47-48
https://doi.org/10.1109/vlsic.1993.920533

Abstract

The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature. This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode. The circuit also features V/sub T/ variation immunity due to the negative feedback effect through the source impedance. This scheme permits battery backup even for giga-scale LSIs.

Keywords

CMOS INTEGRATED CIRCUITS
LARGE-SCALE INTEGRATION
VERY-LARGE-SCALE INTEGRATION
DRAM CHIPS
SWITCHED CIRCUITS
DIGITAL INTEGRATED CIRCUITS

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