Techniques for fast CMOS-based conditional sum adders

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Abstract
Conditional sum adders, CSAs, and carry-lookahead adders, CLAs, both have logarithmic gate depth. However, CLAs require a final add stage while CSAs produce the sum bits in parallel with the final carry bit. For CMOS implementations, the depth advantage of CSA has been difficult to exploit since the traditional structure of CSAs have some heavily loaded internal nodes. We show that the CSA-operation forms a monoid and that all circuit structures, corresponding to parallel prefix algorithms, used with CLA to reduce internal fan-out, are applicable also to CSAs. Furthermore, we show that all time critical computations in a CSA can be performed with monotone functions which allow efficient dynamic CMOS logic to be used. Finally we evaluate a variety of transistor level adder implementations with respect to speed and we show that in almost all cases the CSA has lower delay than its CLA counterpart.

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