A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming
- 1 June 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 9 (3) , 26-44
- https://doi.org/10.1109/40.31476
Abstract
A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.Keywords
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