A Suggestion for a Fast Multiplier

1 February 1964

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers

Vol. EC-13 (1) , 14-17
https://doi.org/10.1109/pgec.1964.263830

Abstract

It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, μsec, and quotients in 3 μsec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.

Keywords

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