A 20ns 64K NMOS RAM

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 226-227
https://doi.org/10.1109/isscc.1984.1156718

Abstract

A 32.6mm²4K×16 NMOS SRAM having a 20ns access time and 30ns cycle time will be covered. The SRAM utilizes a 4 transistor dynamic refresh memory cell with 1.7μm features and single level polycide.

Keywords

MOS DEVICES
DECODING
TIMING
CAPACITANCE
VOLTAGE
CLOCKS
SWITCHES
DRIVER CIRCUITS
FAULT LOCATION
SAMPLING METHODS

This publication has 1 reference indexed in Scilit:

A NMOS 64K static RAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1982