Sun's SPARCstation 1: a workstation for the 1990s

Publisher Website
Google Scholar
Abstract
The architecture and features of the SPARCstation 1 are described and compared with those of other workstations and PCs of approximately the same cost. The heart of the machine is implemented using seven custom CMOS gate arrays plus a single-chip SPARC integer unit and a single-chip SPARC floating-point unit. The architecture of SPARCstation 1 reflects the use of CMOS technology, especially in the design of the SBus, which is SPARCstation 1's memory and I/O expansion interconnect. As a processing engine, SPARCstation 1 provides the user with 12.5 MIPS, 1.4 MFLOPS, and 64 MB of memory. The SBus provides the means for connecting peripheral devices such as IPI (interprocessor interrupt) drives and FDDI interfaces. The SBus accommodates these devices by having a peak bandwidth of 80 MB/s and a sustained bandwidth in the SPARCstation 1 implementation of approximately 25 to 30 MB/s. An optional graphics accelerator, the GX, can render almost 5 Mvectors/s.

This publication has 1 reference indexed in Scilit: