Threshold-voltage instability of n-channel MOSFET's under bias-temperature aging

Abstract
New experimental evidence of positive threshold-voltage shift caused by interface state generation under positive bias-temperature (BT) aging is presented. Interface states were estimated for MOSFET's using low-frequency (8-Hz)C-Vmeasurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time(t) and temperature(T) dependence for threshold-voltage shift (\deltaV_{T}) is represented experimentally as\deltaV_{T}\infin log (t/t_{0}), wheret_{0}^{-1} \infin \exp (-1.0 eV/kT). The positive VTshift appears faster for MOSFET's fabricated with dry O2oxides as gate insulator than for those with HCI oxides. It is also shown that the VTshift is always larger than the flat-band voltage shift caused by interface state generation under negative BT aging. Generated interface states are distributed in the entire forbidden gap, differing from the case of positive BT aging.

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