16 Mb DRAM/SOI technologies for sub-1 V operation

23 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01631918,p. 609-612
https://doi.org/10.1109/iedm.1996.554057

Abstract

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.

Keywords

RANDOM ACCESS MEMORY
LOW VOLTAGE
ISOLATION TECHNOLOGY
CAPACITORS
CMOS TECHNOLOGY
VOLTAGE CONTROL
MOSFET CIRCUITS
SUBSTRATES
ULTRA LARGE SCALE INTEGRATION
LABORATORIES

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