A synthesis-based test generation and compaction algorithm for multifaults

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Abstract
Because of its inherent complexity, the problem of automatic test pattern generation for multiple stuck-at faults (rmtltifaults) has been largely ignored. Recently, the observation that multifault testability is retained by algebraic factorization demonstrated that single fault (and therefore multifault) vector sets for two-level circuits could give complete multifault coverage for multilevel circuits constructed by algebraic factorization. Unfortunately, in using this method the vector set size can be much larger than what, is really required to achieve multifault coverage, and the approach has some limitations in its applicability. In this paper we present several synthesis strategies for the synthesis of flattenable and non-flattenable circuits for complete multifault testability, with associated compaction procedures. We provide experimental results which indicate that a compacted multifault test set derived using the above strategies can be significantly smaller than the test set derived using previously proposed procedures. These results also indicate the substantially wider applicability of our procedures, as compared to previous techniques.

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