Neural network implementation on a FPGA
- 27 August 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 337-342
- https://doi.org/10.1109/afrcon.2002.1146859
Abstract
This work implemented a feedforward neural network on a FPGA (field programmable gate array). A study was conducted to find the minimum precision required to maintain a recognition rate of at least 95% for two characters within an optical character recognition application. To reduce the circuit size, the bit serial architecture was realised to perform the arithmetic operation. This resulted in an optimal use of the FPGA resources.Keywords
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