The rapidly increasing complexity of microelectronic circuits is confronting the designers and manufacturers of integrated circuitry with new technological difficulties. By the end of the decade it may well be possible to pack a million logic gates onto a single chip. But the yield of defect‐free chips falls rapidly with increasing number of components. With current lithographic techniques, the production of custom circuits in small numbers is often uneconomical, and it is widely felt that the semiconductor industry is not meeting the need for such circuits. Furthermore, these lithographic procedures cannot produce large‐area integrated circuits bigger than a few square inches, and their slow turnaround time hinders the design testing necessitated by increasing miniaturization.