Design And Performance Of A Coherent Cache For Parallel Logic Programming Architectures
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10636897,p. 25-33
- https://doi.org/10.1109/isca.1989.714521
Abstract
This paper describes the design and performance of a tightly- coupled shared-memory coherent cache optimized for the ex- ecution of parallel logic programming architectures. The cache utilizes a copy-back write-allocation protocol having five states and a hardware lock mechanism. Optimizations for logic programming are introduced in four software controlled memory access commands: direct-write, exclusive-read, read-purge, and read-invalidate. In this paper we describe these operations and present simulated measurements showing their performance advantage for an architecture of the committed-choice language KL1 The cache optimizations also improve the performance of non-committed-choice languages, such as OR-parallel Prolog. A version of the cache design described here is currently being implemented for ICOT's Parallel Inference Machine (PIM).Keywords
This publication has 10 references indexed in Scilit:
- A characterization of sharing in parallel programs and its application to coherency protocol evaluationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Data buffer performance for sequential Prolog architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A low-overhead coherence solution for multiprocessors with private cache memoriesPublished by Association for Computing Machinery (ACM) ,1998
- The Aurora or-parallel Prolog systemNew Generation Computing, 1990
- Overview of the Parallel Inference Machine Operating System (PIMOS)Published by Springer Nature ,1988
- Overview of the Parallel Inference Machine Architecture (PIM)Published by Springer Nature ,1988
- Cache coherence protocols: evaluation using a multiprocessor simulation modelACM Transactions on Computer Systems, 1986
- Implementing a cache consistency protocolACM SIGARCH Computer Architecture News, 1985
- Using cache memory to reduce processor-memory trafficPublished by Association for Computing Machinery (ACM) ,1983
- Cache MemoriesACM Computing Surveys, 1982