Algorithms for multiplication in Galois field for implementation using systolic arrays

1 January 1988

journal article
Published by Institution of Engineering and Technology (IET) in IEE Proceedings E Computers and Digital Techniques

Vol. 135 (6) , 336-339
https://doi.org/10.1049/ip-e.1988.0045

Abstract

Operations in finite fields find diverse applications. Circuits have been designed for carrying out such operations. In the paper, two circuits that carry out multiplication in GF(2^p) have been presented. These circuits are suitable for implementation using VLSI techniques, and are simpler than existing circuits. The architecture used here is that of systolic arrays and consists of regular interconnection of simple cells.

Keywords

REGULAR INTERCONNECTION
MULTIPLICATION ALGORITHMS
FINITE FIELDS
VLSI TECHNIQUES
GALOIS FIELD
SYSTOLIC ARRAYS

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