An InP HBT low power receiver IC integrating AGC amplifier, clock recovery circuit and demultiplexers
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10647775,p. 205-207
- https://doi.org/10.1109/gaas.1997.628270
Abstract
The authors designed and fabricated a highly integrated and very low power receiver IC for 2.5 Gb/s optical communication. It consisted of an AGC data recovery circuit and demultiplexer, and consumed only 340 mW power. The measured data have validated our design approach and have demonstrated the potential of the InP HBT technology to integrate analog and digital functions for low power and high speed applications. Achieving even lower power is feasible through device scaling. Additional functionality such as multiple data rate, frequency detection, lock indicator and data decoder can be included in future integration.Keywords
This publication has 4 references indexed in Scilit:
- InGaP/GaAs HBT-IC chipset for 10-Gb/s optical receiverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An InP-based HBT fab for high-speed digital, analog, mixed-signal, and optoelectronic ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistorIEEE Journal of Solid-State Circuits, 1996
- A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technologyIEEE Journal of Solid-State Circuits, 1993