Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
- 1 January 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-22 (1) , 46-60
- https://doi.org/10.1109/t-c.1973.223600
Abstract
With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture. The problem is particularly acute for sequential circuits, where there are difficulties in setting and checking the state of the system.Keywords
This publication has 17 references indexed in Scilit:
- A Method for the Design of Fault Detection ExperimentsIEEE Transactions on Computers, 1970
- Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection ExperimentsIEEE Transactions on Computers, 1968
- Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic CircuitsIEEE Transactions on Electronic Computers, 1967
- Diagnosis of Large Combinational NetworksIEEE Transactions on Electronic Computers, 1967
- Design of Sequential Machines with Fault-Detection CapabilitiesIEEE Transactions on Electronic Computers, 1967
- An organization for checking experiments on sequential circuitsIEEE Transactions on Electronic Computers, 1966
- On an Improved Diagnosis ProgramIEEE Transactions on Electronic Computers, 1965
- Fault detecting experiments for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1964
- Derivation of optimum test sequencies for sequential machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1964
- The Diagnosis of Asynchronous Sequential Switching SystemsIEEE Transactions on Electronic Computers, 1962