Self: a self-timed systems design technique

12 March 1987

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 23 (6) , 269-270
https://doi.org/10.1049/el:19870196

Abstract

An asynchronous CMOS circuit technique that can realise both combinatorial and sequential logic is introduced. Circuits so designed exhibit correct operation that is independent of wiring delays. An example of a first-in, first-out (FIFO) memory will be used to illustrate the technique.

Keywords

SEQUENTIAL LOGIC
SELF-TIMED SYSTEMS DESIGN TECHNIQUE
SELF
FIFO MEMORY
ASYNCHRONOUS CMOS CIRCUIT TECHNIQUE
LOGIC DESIGN
COMBINATORIAL LOGIC

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