This report examines the spectrum of architectures from von Neumann to dataflow by proposing a new architecture which is a hybrid of the two paradigms. The analysis attempts to discover those features of the dataflow architecture, lacking in a von Neumann machine, which are essential for tolerating latency and synchronization costs. These features are captured in the concept of a parallel machine language wherein the units of scheduling, called scheduling quanta, are bound at compile time rather than at instruction set design time. It is shown that the combination of dataflow-style explicit synchronization and von Neumann-style implicit synchronization results in an architectural synergism. Using an instruction set which is strictly less powerful than that of the MIT Tagged-Token Dataflow (TTDA), the hybrid architecture can exploit the same kinds of parallelism while executing fewer instructions, demonstrating the power of passing state implicitly between program-counter sequenced instructions. Keywords: Multiprocessors.