A New Automatic Logic Interconnection Verification System for VLSI Design
- 1 April 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 2 (2) , 70-82
- https://doi.org/10.1109/tcad.1983.1270023
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Computational Complexity of Combinatorial and Graph-Theoretic ProblemsPublished by Springer Nature ,2011
- Unified Shapes Checker - A Checking Tool for LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Topological Analysis for VLSI CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- A Fast Backtracking Algorithm to Test Directed Graphs for Isomorphism Using Distance MatricesJournal of the ACM, 1976
- An Algorithm for Subgraph IsomorphismJournal of the ACM, 1976
- A Backtrack Procedure for Isomorphism of Directed GraphsJournal of the ACM, 1973
- An Efficient Algorithm for Graph IsomorphismJournal of the ACM, 1970
- An Appraisal of Some Shortest-Path AlgorithmsOperations Research, 1969
- Algorithm 97: Shortest pathCommunications of the ACM, 1962