Analysis and design of low-phase-noise ring oscillators

1 January 2000

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 289-294
https://doi.org/10.1109/lpe.2000.155301

Abstract

This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.

Keywords

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