High holding voltage C-MOS technology with lightly doped source and drain regions
- 1 April 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 34 (4) , 810-816
- https://doi.org/10.1109/T-ED.1987.23000
Abstract
This work presents the results of measurements and simulations of n-well C-MOS structures fabricated to study the effect of reduced source-drain doping of p-channel MOSFET's on latchup triggering and holding characteristics. It is shown that lighter dopings, degrading the emitter efficiency of the parasitic p-n-p bipolar transistor, lead to improved latchup resistance that can be conveniently traded off versus the induced decrease of MOSFET transconductance.Keywords
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