Theoretical effects of overlap capacitance upon MOS inverter output

1 June 1968

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE

Vol. 56 (6) , 1088-1089
https://doi.org/10.1109/PROC.1968.6461

Abstract

Gate overlap and capacitive feedthrough in digital circuits can cause performance degradation. Effects of overlap on a basic MOSFET inverter are considered. An example shows that the inverter output can be reduced significantly due to capacitive coupling.

Keywords

CAPACITANCE
VOLTAGE
PULSE WIDTH MODULATION INVERTERS
CLOCKS
DEGRADATION
MOSFET CIRCUITS
COUPLING CIRCUITS
CAPACITORS
DELAY
DIGITAL CIRCUITS