Interconnection Technology for Three-Dimensional Integration

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Abstract
The technology of thermally stable and fully planarized multilevel interconnections with selective CVD-W vias and 31P+/11B+ implanted WSi x /TiN/Si contacts has been developed for three-dimensional VLSIs. Via holes with high aspect ratios (about 3) and different depths (0.8–3.0 µm) were completely filled by selective W-CVD and subsequent etch-back, and the surface was planarized to below 0.2 µm using a previously reported interlevel insulation planarization technology. Metal-silicon reactions during high-temperature annealing were eliminated by the use of a TiN thin film (0.08 µm) containing oxygen as a diffusion barrier. By performing an additional 31P+ and 11B+ implantation into the interconnection, the ohmic contacts to n + and p + Si in this structure were also maintained even after annealing at 900°C for 6 hours.