Embedded CELP coding for variable bit-rate between 6.4 and 9.6 kbit/s
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15206149,p. 681-684 vol. 1
- https://doi.org/10.1109/icassp.1991.150431
Abstract
The authors consider the design of a variable-bit-rate CELP (code-excited linear prediction) coder which incorporates the facility of producing an embedded bit stream. This characteristic is particularly attractive for packet transmission where some packets can be lost or rejected whenever they are not received within the maximum allowed delay. The basic scheme used for the investigations is a CELP coder in which the innovation signal is split into three separate contributions. The sum of all contributions, together with the side information, determines the operating bit rate of 9.6 kb/s. The reduced bit rates of 8 and 6.4 kb/s can be achieved, dropping respectively the information relevant to one or two contributions to the innovation signal.Keywords
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